Input and output (I/O) circuits on an integrated circuit (IC) provide communication between external devices and the core logic circuits. In modern microcircuits, the I/O and core circuits operate at different voltages. Typically, modern microcircuits use a higher input/output voltage (VDDIO) of, for example, 3.3 V, 2.5 V, or 1.8 V, while the core supply voltage (VDD) can be of approximately 1.2 V or lower in sub-130 nm process technologies. The higher VDDIO allows interconnection to ICs operating at legacy voltages and potentially improves board level signal noise immunity.
Mitigating radiation effects is important for ICs that are intended for harsh environments such as spacecraft. Ionizing radiation can affect the IC long term reliability through total ionizing dose (TID) effects, which impact individual device characteristics over time. Furthermore, the IC logic state may be temporarily altered to be incorrect by charge collected from ionizing radiation particle strikes, e.g., single event effects (SEE) produced by impinging heavy ions or protons. These particles can also produce a single event transient (SET) that can cause improper logic outputs or timing.
Correct communications into and out of an IC in the presence of ionizing radiation is important, particularly to avoiding placing the IC into an incorrect functional state, known as a single event functional interrupt (SEFI) which may include issuing an inadvertent command, such as erroneously asserting the reset. An I/O SET may also shorten a reference clock edge, which may result in loss of phase loop lock. Specialized radiation hardened processes have typically used silicon on insulator (SOI) substrates. The shorter path length that an ionizing radiation particle can travel in the silicon beneath the active circuits limits the amount of charge that can be collected. Consequently, for these processes, the relatively large I/O circuit capacitances and low-pass characteristics of digital circuits may mitigate SETs. Radiation hardening by design (RHBD) approaches include temporal redundancy to mitigate SETs but these impact the circuit speed.
Radiation effects in complementary metal-oxide-semiconductor (CMOS) circuits are primarily manifest as prompt dose, TID, single event latchup (SEL), and other SEE. TID effects are principally exhibited as long-term degeneration of device characteristics due to positive trapped charge in oxides that are exposed to ionizing radiation. Prompt dose effects are due to the collection of photocurrents produced by incident radiation. The primary IC effect is power rail voltage (rail span) collapse due to inability of the power supply or IC wiring to deliver the required currents.
Total Ionizing Dose Effects:
Total ionizing dose effects are produced when ionizing radiation creates electron-hole pairs within the oxides. These can induce both trapping damage, which affects the subthreshold slope, and threshold voltage (Vth) shifts. Electrons, which are more mobile, can escape, and the holes produce a net positive charge. For commercial processes the core oxide scaling trend, which has reduced thicknesses below 5 nm, eliminates Vth shifts by allowing both holes and electrons to escape the gate oxide before being trapped. Improved oxynitride gate composition has also reduced trapping damage. However, thick-gate transistors are still used in I/O circuits to allow high voltage tolerance and thus legacy voltage compatibility. Consequently, the thicker gate oxide transistors used in I/O circuits, as well as the very thick IC isolation oxides, i.e., shallow trench isolation (STI), remain vulnerable to TID effects in modern microcircuits fabricated on sub 100 nm technology nodes.
TID primarily shifts metal-oxide-semiconductor (MOS) transistor threshold voltage (Vth) downwards. P-Type MOS (PMOS) transistors are affected, but an increase in the parasitic (field) transistor Vth has no deleterious effects. TID produces two primary N-Type MOS (NMOS) transistor leakage paths. Drain-to-source leakage in a single NMOS transistor is produced by a reduction in the Vth at the transistor edges, i.e., the interface between the thin and thick oxides. The second primary leakage current path is created under the STI between diffusion areas, i.e., between NMOS sources or drains at different biases or from an NMOS source/drain diffusion to the N-type well.
SEU and SET in Microcircuits:
SEE logic upsets are manifest as single event upsets (SEU) and single event transients. SEU is due to impinging ionizing particles, such as cosmic rays or protons, generating charge that upsets the logic state of bi-stable storage elements. An SET is a temporary voltage glitch in combinational logic generated by the collection of charge deposited by a massive ionizing particle such as a heavy ion. The glitch to the wrong state is temporary, and its duration is dependent on the linear energy transfer (LET) of the striking ion and the capacitance and current drive of the node struck. Thus, SETs only upset the IC architectural state when captured by a receiving sequential circuit. For higher IC operating frequencies and reduced operating voltages, SET mitigation has become critical, since the amount of charge deposited does not scale, resulting in transient durations of over 1 ns. A sufficient current drive and/or node capacitance can mitigate any SET at the actual large pad drivers in I/O circuits. However, the small receiver, level shifting, and buffering circuits are vulnerable and must be otherwise protected.
Radiation Hardening by Design:
RHBD uses layout techniques to avoid creating or cut off the leakage current flow produced by prolonged TID exposure Annular, or edgeless, transistors apply the same bias across any transistor gate oxide to isolation oxide interface and thus eliminate NMOS transistor drain-to-source leakage increase due to TID. P+ guard rings create a back to back diode structure to interrupt current paths created by trapped positive charge in isolation oxides. Alternating P+ and N+ guard rings protect against latchup due to beyond the rail voltages applied to the pads or in other circuits due to particle strikes.
Recently, due to the dramatically increasing processing costs and greater availability of state-of-the-art commercial foundry capacity, providing radiation hardness solely through design techniques rather than a specialized fabrication process, has garnered increased attention. Previous I/O SEE RHBD Approaches: have focused on field-programmable-gate-array (FPGA) based designs with triple modular redundancy (TMR) I/O circuits, achieved by triplication of the pads and triplication of driving/receiving circuits. Such approaches have been inefficient due to the large increase in area and resources needed to achieve TMR. A need thus exists in the art to develop radiation hardened by design digital input/output circuits and related methods that address such limitations of the current technology.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different figures denote the same elements.
The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “include,” and “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, device, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, system, article, device, or apparatus.
The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
The terms “couple,” “coupled,” “couples,” “coupling,” and the like should be broadly understood and refer to connecting two or more elements or signals, electrically, mechanically or otherwise. Two or more electrical elements may be electrically coupled, but not mechanically or otherwise coupled; two or more mechanical elements may be mechanically coupled, but not electrically or otherwise coupled; two or more electrical elements may be mechanically coupled, but not electrically or otherwise coupled. Coupling (whether mechanical, electrical, or otherwise) may be for any length of time, e.g., permanent or semi-permanent or only for an instant.
“Electrical coupling” and the like should be broadly understood and include coupling involving any electrical signal, whether a power signal, a data signal, and/or other types or combinations of electrical signals. “Mechanical coupling” and the like should be broadly understood and include mechanical coupling of all types. The absence of the word “removably,” “removable,” and the like near the word “coupled,” and the like does not mean that the coupling, etc. in question is or is not removable.